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Why it matters: Samsung’s V-NAND technology has advanced significantly, growing from 24 layers to nearly 300 layers in just over a decade. Although the company has faced significant challenges in additional scaling, it remains confident that it can fit at least 400 layers of flash memory cells into NAND chips. If all goes as planned, mass production could begin by the end of next year.
Samsung’s 9th-generation 280-layer V-NAND flash memory has only recently entered mass production, with the first commercial products expected to hit store shelves next year. However, according to the Korea Economic Daily, the company is already setting ambitious targets for its 10th-generation 400-layer V-NAND technology.
Competition in the space has intensified in recent years, driven in large part by the increasing demands of AI applications, along with a growing consumer appetite for larger and more affordable flash storage.
Samsung currently holds a leading 37 percent market share, but maintaining that position is becoming increasingly challenging as competitors like Micron, YMTC, SK Hynix, and Kioxia accelerate their development of higher-density 3D NAND.
SK Hynix plans to begin manufacturing 400-layer NAND by the end of 2025, with full-scale production expected in the first half of 2026. This has prompted Samsung to target the same timeline, as its smaller Korean rival has gained significant market share over the past two years.
Stacking 400 or more layers of NAND is no easy feat, as scaling beyond 300 layers has already posed challenges to the reliability of early prototypes. To tackle this, Samsung plans to employ a Tri-Level Cell (TLC) architecture alongside a new technology called Bonding Vertical NAND (BV NAND), which separates memory cells and peripheral circuitry onto different wafers, which are then bonded together in a vertical structure.
This approach will also help Samsung achieve higher manufacturing yields compared to those of the Cell over Periphery (CoP) NAND design. The company claims it can reach densities of 28Gb/mm², or 1Tb (128GB) per die, which is only slightly lower than the density achieved with a 9th-generation Quad-Level Cell (QLC) architecture. Additionally, the 5.6Gb/s data rate per pin provides a significant performance boost over the 3.2Gb/s maximum achievable with the previous design.
In theory, future Samsung SSDs could reach capacities of up to 16TB, with speeds approaching the limits of a PCIe 5.0 x4 interface in sequential reads and writes.
Samsung will present this promising new V-NAND architecture in more detail at the upcoming International Solid-State Circuits Conference in February 2025.
